Traditional ADCs are built using analog circuitry that quantize the input signal in the voltage domain (Fig. 1(a)). As technology scales, voltage dynamic range decreases and design difficulties for analog circuits arise. Alternatively, time resolution is improving as technology scales. VCO-based quantizers are highly digital circuits which quantize in the time domain rather than in the voltage domain (Fig. 1(b)), and thus are becoming more attractive in deeply scaled technologies. Early work has used a simple digital counter to quantize the VCO signal. However, issues with the counter "missing" VCO transitions near the sampling clock edge have led to the use of a frequency-to-digital converter (FDC) as the quantization circuit (Fig. 2(a)). The FDC has been widely adopted due to its inherent first order noise shaping characteristic, however, it places a restriction that the sampling frequency must be twice that of the maximum VCO frequency. Another digital time quantization using time-to-digital converters (TDCs) have been traditionally used in phase-locked loops to quantize the VCO phase error, but have not been applied to VCO-based ADCs. This work proposed the use of a delay-line based TDC to quantize the VCO signal (Fig. 2(b)), which only requires that the sampling rate be twice that of the input signal to the VCO. Our results indicate that the VCO nonlinearity (kv) remains the primary bottleneck of these types of quantizers, causing large spurs in the output spectrum (Fig. 3). While both quantizers responded similarly to VCO nonlinearity and phase noise, the TDC was less sensitive to sampling clock jitter. These results were published into a short monograph.
Students Involved: S. M. McDonnell