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High-Speed LVDS Transceivers

Emerging high speed mixed signal circuits require effective means of custom data I/O to support ever-increasing sampling rates. The traditional means of high speed chip-to-chip communication employs a low voltage differential signal (LVDS) scheme. LVDS receivers require either a robust rail-to-rail input stage to accommodate large variation in common mode or a large, off-chip capacitor to couple the incoming signal while allowing the desired common mode to be set on-chip. Rail-to-rail input stages have become less common in advanced processes because of the low breakdown voltage associated with these nodes. The alternative architecture, making use of off-chip coupling capacitors, uses a coding scheme to ensure an adequate number of data transitions. While effective, this method has substantial area and data rate overhead. The proposed architecture uses small, on-chip coupling capacitors before the LVDS amplifier stage to set the common mode on-chip. This topology is advantageous because it removes the need for a rail-to-rail input stage, allows for optimum biasing of the receiver amplifier without regard for the input common mode, and removes the need for discrete components. Data feedback, instead of a coding scheme, is used to ensure lower bit transition rates, which do not sufficiently couple through the on-chip capacitors, are accurately received.

Students Involved: J. J. McCue