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Digital Calibration Schemes for GHz-Speed DACs

Modern communication systems require high-Speed high-resolution data converters with sufficient linearity to transfer complex modulations schemes. The current steering architecture is employed due to its switched current configuration which benefits from scaling CMOS processes that offer an improvement in transistor switching speed (i.e. f_T) and reduced device capacitance allowing wideband frequency synthesis with minimal slewing errors. However, an increase in random process mismatch and reduced output impedance generates nonlinear amplitude offsets and timing glitches in the conversion process. The amplitude mismatches effect DAC linearity across the entire Nyquist band, while timing mismatch has a frequency dependent degradation limiting DAC linearity above a few 100 MHz operating frequency. Calibration is required to reduce the mismatch and 

maintain linearity. Amplitude error calibration has been well developed and silicon proven over the year, however, timing error calibration has just starting being explored. This research hence, focuses on robust and hardware-efficient built in time error calibration techniques.

 
A DAC model has been developed to assist in the design of a new timing

calibration technique which reduces timing mismatches through modulation of the clock signal’s delay to the DAC retiming latches (termed adaptive clock delay (ACD) calibration). For verification a 14-bit DAC designed in 130nm BiCMOS process (Fig. 1) is designed and fabricated. The DAC uses a 7-bit parallelized LVDS input data stream to generate 14-bits of input data and contains calibration measurement with amplitude and ACD calibration routines. Simulation results show the ACD technique reduces the effect of timing mismatches and significantly improve DAC linearity (Fig. 2) across
operating frequency. Measurement results are pending.


Students Involved: S. M. McDonnell